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Opinión (6)
Only syntax, use as a reference not as a first text on VHDL
This book can only be used as a reference.
Great Intro to the VHDL Language
I am an experienced Verilog HDL user and expert logic designer.
let the rating be your judge
A competent text for VHDL language & syntax, but not intended for hardware design.
dont listen to others
Don't listen to the other reviews of this book which give it poor ratings.
This Book Is Not Good For Students
This book only suitable for someone who has already had the idea of programming VHDL.
should be titled as "The SYNTAX Guide to VHDL"
This was the required book for our VHDL class in EE.